Adding a second PIA to the Atari 8-Bit

I agree with you 100%. Just remember, there are multiple solutions out there for just about everything for our Atari's from memory upgrades, OS upgrades, Cart or PBI based HDD, etc., etc., and just because someone is creating a new Atarinet or AtariLAN or whatever, through the SIO doesn't mean others can't do something different and maybe better through controller ports and extra PIA's too. I'd much rather do it that way as, like you said, I have so much working via SIO already and there will be conflicts.

Just like I would rather have the new on-line Dragon "cart" PBI version instead of the cartridge port version both of which are concurrently being developed by different people, that way I can use my SDX cart and MyIDE II carts still while using Dragon communications through the PBI which only has to share with my Syscheck board there for extended memory. Even though daisy-chaining of the SIO and pass-thru of the PBI and cart ports are possible, spreading devices and communications out to all available I/O possibilities sounds the best to me, with the least chance of conflict.

 

This is one thought on how to add additional I/O chips. PIA ACIA VIA etc.
note that the Atari 6520, is pin compatiable with the 6821
Previously posted on Atari Sector but this is my own work, although I'm sure others including Tim have described something very similar (adding an UART.)

 

Whilst its not something I'm into I just love the fact people like Thomas Cherryholmes (think that is the spelling) are doing all these wonderful things, WiFi on an Atari, who would have thunk it.

The only issue for me is that I find being with my router on gives me a headache over time and my face feels like its roasting, I have a mate who suffers very badly with this and has tried to have his new Smart meter removed as he can't even sleep properly now.

Electromagnetic hypersensitivity (EHS) I believe is what its called.

But that aside I love all these side projects to use these old machines as new, be it an Atari or Oric etc its so good that folks like yourself are taking them past what was thought to be their final frontier (I had to do it) and doing things that never exited back then.

Good luck Tim and others....

 

Wow that was a long post Tim. and about to do the same

I'll add my thoughts. Firstly the SIO route is very limited due to the Serial Buss Speed, and would only ever be as high as any other High Speed SIO device. And of course stops anything else going on, due in main to it being 'Software driven' so can only go as fast as the combination of CPU and Pokey allows.

You can by the way use MIDI as a networking transport, and allows I think 16 users all at the same time Network speed is 31-32KBit's have a look Here https://ataribits.weebly.com/midi.html

Going back to networking, although I've not really looked at either of those described, I do have 1st hand knowledge of using both the ESP8266 & its bigger brother the ESP32 for networking sensors and controllers around the Home.

To be able to use a Wi-Fi connection that follows the current protocols in general use would tie up a 6502, and be very slow, however by adding a secondary Serial or Parallel port that squirts data back and forth to one of these chips is a good way to use the ESP chips power to run the say TCP/IP or HTTP etc. 'stack'

The Atari, only commanding the unit to select the protocol, and then the data, the send and reply being dealt with by the ESP, and providing the data back to the Atari. The ESP acting as a buffer.

I would guess a modern produced VIA would be the best route to add 65c22 as has the addition of two timer counters above and beyond the 65c21 (6821 or 6520 PIA) at a pinch the ACIA 65c51 adds a full proper UART with baud rate generation etc.

I still think the VIA is a better option though. I'll have a look.

whatever way is chosen both code for the ESP and for the Atari is required, I wouldn't put myself as a competent programmer in 6502, a bit better C or Assembler on AVR chips. (A little bit with the ESP added to Arduino's IDE.

Really though I'm a hardware man.

 

Paul I've heard of EHS but thankfully never experianced similar, I guess lucky as I've worked on many projects from high Power AM/FM broadcast transmitters and lowered powered DAB to Mobile phone base stations, including my home built RF amplifiers to bounce VHF radio signals off the moon. (and a really big antenna array needed)

Nothing Atari there though ...

 

I've had a look at this and I don't really understand why he made it so awkward an upgrade. Nor why he chose not to use the 2nd Port on the additional PIA, it makes no sense to add something and not use it.

Peter's ATR image maybe of some use however.

For an 800, whatever way you upgrade it, you have to be able to get the new port lines out, that means in general metal work, the only other way would be to mash up the plastics in the left cartridge port area and have something there. Personally a hole in the left side of the metal screen, going out to the empty area within the left side of the computer with either case mods or cable slotted through the existing grills.
I'll also mention that Incognito may mess with this although out seems outside the address range I'll have to check
When I'm back on my feet I'll have a go with the BOOT ATR in Altirra.

 

I've been finding out a little more about some of the upgrades that are usually added, U1MB & Incognito both use Additional address registers for there own use at D380-D3FF in addition they also expose RAM, When PBI ROM is enabled, 895 bytes of I/O RAM are also exposed: 191 bytes at $D100-D1BE, 192 bytes at $D500-D5BF, and 512 bytes at $D600-D7FF. These bytes are from dedicated memory not otherwise accessible due to being shadowed by the I/O address region. When I/O RAM is active, these address ranges are blocked. ( So I guess no problem adding hardware here as the I/O line will not be active whilst the PBI BIOS uses the area as RAM)
VBXE also has registers at either D640-D65F or D740-D75F so limitations here.
SIDE/SIDE2 MYIDE etc, use D1xx
Cartridges SIDE2, OSS, SPARTADOX and many others can all use areas of D5xx
I've found all of this information in Avery Lee's Altirra Hardware Reference Manual.

With this in mind I'll re design my circuit to make sure the region D380-D3FF is decoded so that inadvertant writes cannot affect the control registers used by the U1MB & Incognito, so allowing an additional PIA or more to be used in upgraded machines.
Still not myself at the moment so lots of reading and only a bit of taking pictures and occationally online.
Not even tried the PokeyMAX out I've had it 3 days or so, got so far and needed some rest.

 

I am on the edge of my seat @Graham , awaiting on you then for my PIA upgrade in the 800. I wasn't planning on a PIA upgrade this round anyway. Right now it's just Incognito, stereo Pokey, and outputs for stereo Pokey and video out the back. Round two would involve making a PBI and the PIA upgrade with extra ports. Round 3 will be a Sophia 2 and a VGA port (DVI is out of the question, for me, as pixels are forced to be square with DVI which means screens not in the proper aspect which is unacceptable to me), but the Sophia 2 was just announced on AA and is not available yet.

 

I'll make sure I get around to it
This attachment is incorrect since I've been reading as I need to add A7 address line to make sure the D380-D3FF region is decoded, any writes to this ouside the U1MB BIOS or PBI BIOS needed to be disabled and this hasn't been. I've just ignored them..

 

With piggy-backed Pokeys, or any dual Pokey board, only a very select few pins are shared by the second chip, and the 74LS chip used with the upgrade allows them to work together and not step on each other's toes. It definitely wouldn't work if all the pins were connected to each other. The rest is all software driven. Now like you with hardware, I'm that way still with software (though I'm learning), but my understanding is the second chip has it's own addresses programmed.

 

Hi Tim
Yep the second, piggy backed chip, say Pokey, will have a common clock, data and control lines except the Chip Select, likewise all Pokeys 'port' lines such as audio, keyboard scan, and interupt, are left disconnected, the Chip select line for the piggy back chip has additional logic to select the original or the secondary Pokey, usually address line four A4
So with this either high or low it selectts the original Pokey, or the piggy backed one depending on the address. I'm out at the moment so can't check the lines but I'll try and write something up, thats easy for people to understand
The second Pokey as a stereo only addition obviously has its Audio routed out the computer, If you wanted to the keyboard lines could be repurposed for something else a secondary keyboard or something else as you have a few lines that could be controlled separately if you wanted to. Just need the software to issue the commands to the new register addresses in the second Pokey.

 

Same thing; every new chip installed has it's own addressing. Piggy-backing is just easier sometimes than building a support board for the new chip(s)

 

I Found this recently on AA https://atariage.com/forums/topic/307567-pias-6520-they-are-not-made-the-same-after-all/

There is also reference to what speed the PIA port lines can be fed data due to the way the chip was designed, with some later production chips perhaps being better than others.
Tim also worth noting this :-
I think I stumbled upon this issue once, long time ago (1992?). I connected two Ataris via a cable connected to the joystick port 0 of both machines. I used an asynchronous protocol to send data. Out of the 4 bits available, I used two as data bits and the two others for handshaking.
I was testing it sending GR.8 bitmaps from the one Atari to the other.
Everything worked fine until I decided, to save (IIRC) 2 cycles in the handler on either side, that I should use 0 instead of 1 as the handshaking value (previously 0 on the handshaking line meant that no data is available on the data lines, 1 that it is). And then the receiver started to lose "1"s which were set onto the data lines together (one STA) with the zeros on the handshaking lines by the sender. Some 1s sent were received as 0s.
My conclusion then was that apparently the zeros are transmitted faster than ones via the PIA port

This posted by Drac030 3June

 

And that's why (controller ports 1-4, PIA 0-3) I'm adding a second PIA to both the 800 and 1200XL, as with either one, I'll have the possibility of 6 or more ports to use with my Atarilab Interfaces, regardless of "mode*," though at first I only intend to add two more ports each, so a total of 6 physical ports on the 800 and 4 on the 1200XL, as a starting point. With the theoretical possibility of 6-8 ports depending on the computer and mode. The more ports the merrier! For networking and control of my experiments and prototypes.Of course the 1200XL will have PIA ports 0 & 1 and 4 & 5 and the 800 0-5 physically. PIA ports 6 & 7 (2 & 3 on the second PIA) will not be used on either machine at first. Technically, I think port 3 could be accessed and used on XL/XE machines as I believe the OS only needs port 2 for extended memory beyond 48K, and be XE and Rambo compatible up to 1024K (1088K).

*W/Incognito 4 ports are available in Colleen mode and 2 ports in XL/XE mode with one PIA.

 

Entirely with you on the use of an 800, just be aware that some of the PIA chips appear a little flaky, however as yours will mainly be used for external control and sensors high speed shouldn’t be an issue, However that's not the case from Tim's perspective of using for as high a speed networking as possible.

I've attached an updated PDF of the circuit that I'll be testing.

It takes into account all of the modern additional upgrades commonly used. but hey I don't know all the possible older ones from years back.

The main one that could cause issues is the U1MB / Incognito as this uses the upper 128 Bytes of the decoded space D380 to D3FF for its own use, registers, memory access used by it's routines etc.

That means to add an additional PIA we can just use the next address line that selects between upper and lower blocks of D3xx

So, I have to use A7 to determine the upper area used by U1MB etc. and the lower that’s safe to use, this is attached to one of the Enable lines on the decoder, in this case a 3 to 8 line decoder (74LS138) connected to address lines A4, A5, A6 missing out A3, A2, A1, A0 allows for 8 blocks of address's that are 16 bytes long this just allows much more complex external chips to be added above and beyond a PIA which only needs 4 bytes of space, two bytes for the registers and two for Ports A & B. using A0 & A1

With the current decoding you can genuinely add an additional 7 PIA's or other chips if you so wanted, that would be fully decoded into their own address space. PH2 would need buffering however

The original PIA will be addressed fully at D300-D303,
Adding a PIA as the 2nd address block would use D310-D313, the third D320-D323
That’s wasting 12 address spaces but allows chips with additional Register Select lines PIA has RS0 & RS1 only.

If we wanted to add the 65c22 VIA this uses RS0, RS1, RS2 & RS3 so having up to 16 registers, these would connected to A0, A1, A2 & A3 say at block D330-D33F using all 16 bytes, that’s why I've left a gap, so other chips could be used with the same circuit.

As I've been around computers and designing stuff so long I find this easy, however each to their own, I don't make a good forklift driver nor a farmer, lawyer, etc.

I'm happy to try and help people understand where I can, so those that are put off by this I'm happy for you to contact me perhaps by PM I hope this doesn’t offend anyone as it's certainly not intended that way.

 

Matt how does an additional 28 Atari Lab interfaces sound ?

If you really wanted I could design something for an additional 31 PIA's, or 128 Atari Lab interfaces just not sure where you would fit them all...

 

I mentioned it but didn't post any circuit as such.
Best I do so .. wonder if it's worth conacting Drac030 see if he has any software his willing to share.
http://drac030.krap.pl/en-main.php
Or His on AA